Ferroelectric tunnel junction devices with metal-FE interface layer and methods for forming the same

ABSTRACT

A memory device, transistor, and methods of making the same, the memory device including a memory device including: a ferroelectric (FE) structure including: a dielectric layer, an FE layer disposed on the dielectric layer, and an interface metal layer disposed on the FE layer, in which the interface metal layer comprises W, Mo, Ru, TaN, or a combination thereof to induce the FE layer to have an orthorhombic phase; and a top electrode layer disposed on the interface metal.

RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent ApplicationNo. 63/042,600 entitled “Metal-FE interface in Ferroelectric TunnelJunctions”, filed on Jun. 23, 2020, the entire contents of which arehereby incorporated by reference for all purposes.

BACKGROUND

Ferroelectric (FE) memory is a candidate for next generationnon-volatile memory benefits due to its fast write/read speed and smallsize. However, it may be difficult to achieve a desired crystalstructure when growing FE layers on commonly utilized semiconductordevice materials. Various materials may be used to form the FE layerthat may improve the FE properties such as coercivity (E_(c)), remanentpolarization (P_(r)), hysteresis loop squareness (saturation remanencedivided by saturation magnetization), etc. In particular, varioustechniques and materials may be used to obtain high orthorhombiccrystalline phase FE layer in order to obtain good FE properties.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A is a vertical cross-sectional view of a first exemplarystructure prior to formation of an array of thin-film transistors (TFTs)according to an embodiment of the present disclosure.

FIG. 1B is a vertical cross-sectional view of the first exemplarystructure during formation of the array of fin back gate field effecttransistors according to an embodiment of the present disclosure.

FIG. 1C is a vertical cross-sectional view of the first exemplarystructure after formation of upper-level metal interconnect structuresaccording to an embodiment of the present disclosure.

FIGS. 2A-2H are each vertical cross-sectional views illustrating thesequential steps of manufacturing a memory cell, according to variousembodiments of the present disclosure.

FIG. 3A is a vertical cross-sectional view illustrating the memory cellformed according to an alternative embodiment method of the presentdisclosure.

FIG. 3B is a vertical cross-sectional view illustrating a memory cellformed according to another alternative embodiment method of the presentdisclosure.

FIGS. 4A-4G are each vertical cross-sectional views illustrating thesequential steps of manufacturing a transistor, according to variousembodiments of the present disclosure.

FIGS. 5A and 5B are vertical cross-sectional views illustrating thesteps of an alternative method of manufacturing a transistor, accordingto various embodiments of the present disclosure.

FIGS. 6A-6C are sequential vertical cross-sectional views illustratingthe sequential steps of manufacturing a transistor, according to variousalternative embodiments of the present disclosure.

FIG. 7A is a partially transparent perspective view of a transistoraccording to various embodiments of the present disclosure

FIG. 7B is a vertical cross-sectional view along line B-B of FIG. 7A.

FIG. 7C is a vertical cross-sectional view taken along line C-C of FIG.7A.

FIG. 8 is a vertical cross-sectional view of a memory device, accordingto various embodiments of the present disclosure.

FIG. 9 is a block diagram illustrating a method of forming a memory cellaccording to various embodiments.

FIG. 10 is a block diagram illustrating a method of forming a transistoraccording to various embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. Unless explicitly statedotherwise, each element having the same reference numeral is presumed tohave the same material composition and to have a thickness within a samethickness range.

The present disclosure is directed to ferroelectric (FE) device, andspecifically, to memory cells, transistors, and memory structures thatinclude thin interface metals deposited between FE layers and topelectrode metals. The metal-FE interface plays a significant role indetermining the FE crystalline phase. FE properties such as coercivity(E_(c)), remanent polarization (P_(r)), hysteresis loop squareness(saturation remanence divided by saturation magnetization), etc. may begreatly influenced by the materials with which the FE layer formsinterfaces. In particular, for HfO based ferroelectric materials, highorthorhombic crystalline phase may be implemented to obtain good FEproperties. In conventional FE devices, the dielectric and/or top metalin contact with the FE layer may not provide a good interface to inducethe FE for forming the orthorhombic crystalline phase.

Memory devices include a grid of independently functioning memory cellsformed on a substrate. Memory devices may include volatile memory ornonvolatile (NV) memory cells. In contrast to volatile memory cells thatrequire constant power to retain their memory values, nonvolatile memorycells are capable of retaining information when power is not appliedthereto. For example, computers including nonvolatile memory cells donot need to be booted up when switched on.

Emerging nonvolatile memory technologies may include resistiverandom-access memory (RRAM or ReRAM), magneto-resistive random-accessmemory (MRAM), ferroelectric (FE) random-access memory (FRAM, F-RAM, orFeRAM), and phase-change memory (PCM), for example.

FRAM is a random-access memory that utilizes memory cells that include aFE material to store information as FE polarization. An FE material hasan equilibrium-state bulk electric dipole moment. This occurs in solidceramics when ground state crystal structure involves spatial separationof ionic charges, and the unit cell lacks a center of symmetry.Nanoscale alignment of the microscopic electric dipole moments isresponsible for bulk ferroelectric behavior. Typically, the magnitude ofthe dipole polarization and its orientation may be controlled byapplication of modest external electric fields. The change inorientation may be a good indication of the stored value.

FRAM is commonly organized in single-transistor, single-capacitor(1T/1C) or two-transistor, two-capacitor (2T/2C) configurations, inwhich each memory cell includes one or more access transistors. Thenon-volatility of an FRAM is due to the bi-stable characteristic of theFE material in the cell capacitor(s). The cells are typically organizedin an array, such as folded-bit line, open-bit line architectures, etc.,wherein the individual cells are selected by plate line and word linesignals from address decoder circuitry, with the data being read from orwritten to the cells along bit lines using sense amp circuits. Forexample, in an open-bit line architecture, the bit-lines may be dividedinto multiple segments, and differential sense amplifiers may be placedin between bit-line segments. Because the sense amplifiers may be placedbetween bit-line segments, to route their outputs outside the array, anadditional layer of interconnect placed above those used to constructthe word-lines and bit-lines may be required. The folded bit-line arrayarchitecture routes bit-lines in pairs throughout the array. The closeproximity of the paired bit-lines may provide superior common-mode noiserejection characteristics over open bit-line arrays. Folded-bit linearchitecture may be favored in modern DRAM ICs for its superior noiseimmunity. This architecture is referred to as folded because it takesits basis from the open array architecture from the perspective of thecircuit schematic. The folded array architecture appears to remove DRAMcells in alternate pairs (because two DRAM cells share a single bit-linecontact) from a column, then move the DRAM cells from an adjacent columninto the voids.

FRAM memory cells may include a FE tunnel junction (FTJ). Generally, aFTJ may include a metal-FE-metal (MFM) structure, including an FE layerdisposed between two metallic layers (e.g., electrodes). However, someFTJ's may include metal-FE-insulator-metal (MFIM) structure, where adielectric layer is disposed between the FE layer and one of themetallic layers. In particular, the MFIM structure may provide improvedcharge response, as compared to the MFM structure.

Ferroelectric field effect transistors (FeFETs) are emerging devices, inwhich a FE layer is utilized as a gate insulating layer between a gateelectrode and a channel region of an underlying semiconductor layer.Permanent electrical field polarization in the FE layer causes this typeof device to retain the transistor's state (on or off) in the absence ofany electrical bias.

The FE properties of an FE layer, such as coercive field (Ec), remnantpolarization (Pr), polarization-electric field (P-E) loop squareness,etc., may depend upon the crystal structure of the FE layer. The crystalstructure of the FE layer may further depend upon the materials in whichthe FE layer is directly contacting to form an FE interface. Inaddition, the crystal structure of a FE layer may be greatly influencedby the substrate upon which an FE layer is grown. In particular, forhafnium oxide (HfO)-based ferroelectric materials, good FE propertiesmay be dependent upon having a well-formed orthorhombic crystallinephase. For example, FE materials, such as hafnium oxide doped Zr,require a strong orthorhombic phase to exhibit high polarization andcoercive field. Both of these properties impact the FE device's abilityto maintain data in memory. However, a dielectric and/or top metal incontact with the FE may not provide good interfaces to induce the FE forforming the orthorhombic phase. Certain metals may promote the growth ofthe desired crystal phase within the FE. However, some of these metalsat high thicknesses may not be ideal for integration in an FE-baseddevice. For example, some of these metals may be difficult to etch, havehigh resistivity, etc. Thus, various embodiments address these issues byimplementing a thin metal layer to induce an orthorhombic phase in theFE. A metal, such as to form a top electrode, may be disposed over themetal interface layer to cap the FE structure. The metal top electrodelayer may be more conducive to device processing.

Accordingly, various embodiments provide methods of forming FEstructures having improved FE properties, and transistors and memorycells including the same. In particular, various embodiments provide FEstructures including an interface metal layer deposited on aferroelectric layer, in which the interface metal may induce theformation of an orthorhombic crystal structure between an FE layer and ametal layer. In various embodiments, an interface metal may be depositedon top of an FE layer to induce a strong orthorhombic phase in the FE. Atop metal with lower resistivity may then be deposited on top of theinterface metal to lower the total resistance of the FE structure. Thethin interface metal between the FE layer and top metal layer maypromote the formation of an orthorhombic crystal phase in the FE.

FIG. 1A is a vertical cross-sectional view of a first exemplarystructure prior to formation of an array of memory devices according toan embodiment of the present disclosure. Referring to FIG. 1A, a firstexemplary structure according to an embodiment of the present disclosureis illustrated prior to formation of an array of memory structures,according to various embodiments of the present disclosure. The firstexemplary structure includes a substrate 8 that contains a semiconductormaterial layer 10. The substrate 8 may include a bulk semiconductorsubstrate such as a silicon substrate in which the semiconductormaterial layer continuously extends from a top surface of the substrate8 to a bottom surface of the substrate 8, or asemiconductor-on-insulator layer including the semiconductor materiallayer 10 as a top semiconductor layer overlying a buried insulator layer(such as a silicon oxide layer). The exemplary structure may includevarious devices regions, which may include a memory array region 50 inwhich at least one array of non-volatile memory cells may besubsequently formed.

For example, the at least one array of non-volatile memory cells mayinclude resistive random-access memory (RRAM or ReRAM),magnetic/magneto-resistive random-access memory (MRAM), FeRAM, andphase-change memory (PCM) devices. The exemplary structure may alsoinclude a peripheral logic region 52 in which electrical connectionsbetween each array of non-volatile memory cells and a peripheral circuitincluding field effect transistors may be subsequently formed. Areas ofthe memory array region 50 and the logic region 52 may be employed toform various elements of the peripheral circuit.

Semiconductor devices such as field effect transistors (FETs) may beformed on, and/or in, the semiconductor material layer 10 during afront-end-of-line (FEOL) operation. For example, shallow trenchisolation structures 12 may be formed in an upper portion of thesemiconductor material layer 10 by forming shallow trenches andsubsequently filling the shallow trenches with a dielectric materialsuch as silicon oxide. Other suitable dielectric materials are withinthe contemplated scope of disclosure. Various doped wells (not expresslyshown) may be formed in various regions of the upper portion of thesemiconductor material layer 10 by performing masked ion implantationprocesses.

Gate structures 20 may be formed over the top surface of the substrate 8by depositing and patterning a gate dielectric layer, a gate electrodelayer, and a gate cap dielectric layer. Each gate structure 20 mayinclude a vertical stack of a gate dielectric 22, a gate electrode 24,and a gate cap dielectric 28, which is herein referred to as a gatestack (22, 24, 28). Ion implantation processes may be performed to formextension implant regions, which may include source extension regionsand drain extension regions. Dielectric gate spacers 26 may be formedaround the gate stacks (22, 24, 28). Each assembly of a gate stack (22,24, 28) and a dielectric gate spacer 26 constitutes a gate structure 20.Additional ion implantation processes may be performed that use the gatestructures 20 as self-aligned implantation masks to form deep activeregions. Such deep active regions may include deep source regions anddeep drain regions. Upper portions of the deep active regions mayoverlap with portions of the extension implantation regions. Eachcombination of an extension implantation region and a deep active regionmay constitute an active region 14, which may be a source region or adrain region depending on electrical biasing. A semiconductor channel 15may be formed underneath each gate stack (22, 24, 28) between aneighboring pair of active regions 14. Metal-semiconductor alloy regions18 may be formed on the top surface of each active region 14. Fieldeffect transistors may be formed on the semiconductor material layer 10.Each field effect transistor may include a gate structure 20, asemiconductor channel 15, a pair of active regions 14 (one of whichfunctions as a source region and another of which functions as a drainregion), and optional metal-semiconductor alloy regions 18.Complementary metal-oxide-semiconductor (CMOS) circuits 75 may beprovided on the semiconductor material layer 10, which may include aperiphery circuit for the array(s) of transistors, such as thin filmtransistors (TFTs), and memory devices to be subsequently formed.

Various interconnect-level structures may be subsequently formed, whichare formed prior to formation of an array of fin back gate field effecttransistors and are herein referred to as lower interconnect-levelstructures (L0, L1, L2). In case a two-dimensional array of TFTs andmemory devices are to be subsequently formed over two levels ofinterconnect-level metal lines, the lower interconnect-level structures(L0, L1, L2) may include a contact-level structure L0, a firstinterconnect-level structure L1, and a second interconnect-levelstructure L2. The contact-level structure L0 may include a planarizationdielectric layer 31A including a planarizable dielectric material suchas silicon oxide and various contact via structures 41V contacting arespective one of the active regions 14 or the gate electrodes 24 andformed within the planarization dielectric layer 31A. The firstinterconnect-level structure L1 includes a first interconnect leveldielectric (ILD) layer 31B and first metal lines 41L formed within thefirst (ILD) layer 31B. The first (ILD) layer 31B is also referred to asa first line-level dielectric layer. The first metal lines 41L maycontact a respective one of the contact via structures 41V. The secondinterconnect-level structure L2 includes a second (ILD) layer 32, whichmay include a stack of a first via-level dielectric material layer and asecond line-level dielectric material layer or a line-and-via-leveldielectric material layer. The second (ILD) layer 32 may have formedthere within second interconnect-level metal interconnect structures(42V, 42L), which includes first metal via structures 42V and secondmetal lines 42L. Top surfaces of the second metal lines 42L may becoplanar with the top surface of the second (ILD) layer 32.

FIG. 1B is a vertical cross-sectional view of the first exemplarystructure during formation of the array of TFTs and/or memory cellsaccording to an embodiment of the present disclosure. Referring to FIG.1B, an array 95 of non-volatile memory cells and selector devices, suchas TFT selectors, may be formed in the memory array region 50 over thesecond interconnect-level structure L2. The details for the structureand the processing steps for the array 95 of non-volatile memory cellsand TFT selector devices are subsequently described in detail below. Athird (ILD) layer 33 may be formed during formation of the array 95 ofnon-volatile memory cells and TFT selector devices. The set of allstructures formed at the level of the array 95 of non-volatile memorycells and TFT selector devices transistors is herein referred to as athird interconnect-level structure L3.

FIG. 1C is a vertical cross-sectional view of the first exemplarystructure after formation of upper-level metal interconnect structuresaccording to an embodiment of the present disclosure. Referring to FIG.1C, third interconnect-level metal interconnect structures (43V, 43L)may be formed in the third (ILD) layer 33. The third interconnect-levelmetal interconnect structures (43V, 43L) may include second metal viastructures 43V and third metal lines 43L. Additional interconnect-levelstructures may be subsequently formed, which are herein referred to asupper interconnect-level structures (L4, L5, L6, L7). For example, theupper interconnect-level structures (L4, L5, L6, L7) may include afourth interconnect-level structure L4, a fifth interconnect-levelstructure L5, a sixth interconnect-level structure L6, and a seventhinterconnect-level structure L7. The fourth interconnect-level structureL4 may include a fourth (ILD) layer 34 having formed therein fourthinterconnect-level metal interconnect structures (44V, 44L), which mayinclude third metal via structures 44V and fourth metal lines 44L. Thefifth interconnect-level structure L5 may include a fifth (ILD) layer 35having formed therein fifth interconnect-level metal interconnectstructures (45V, 45L), which may include fourth metal via structures 45Vand fifth metal lines 45L. The sixth interconnect-level structure L6 mayinclude a sixth (ILD) layer 36 having formed therein sixthinterconnect-level metal interconnect structures (46V, 46L), which mayinclude fifth metal via structures 46V and sixth metal lines 46L. Theseventh interconnect-level structure L7 may include a seventh (ILD)layer 37 having formed therein sixth metal via structures 47V (which areseventh interconnect-level metal interconnect structures) and metalbonding pads 47B. The metal bonding pads 47B may be configured forsolder bonding (which may employ C4 ball bonding or wire bonding), ormay be configured for metal-to-metal bonding (such as copper-to-copperbonding).

Each (ILD) layer may be referred to as an ILD layer 30. Each of theinterconnect-level metal interconnect structures may be referred to as ametal interconnect structure 40. Each contiguous combination of a metalvia structure and an overlying metal line located within a sameinterconnect-level structure (L2-L7) may be formed sequentially as twodistinct structures by employing two single damascene processes, or maybe simultaneously formed as a unitary structure employing a dualdamascene process. Each of the metal interconnect structure 40 mayinclude a respective metallic liner (such as a layer of TiN, TaN, or WNhaving a thickness in a range from 2 nanometers (nm) to 20 nm) and arespective metallic fill material (such as W, Cu, Co, Mo, Ru, otherelemental metals, or an alloy or a combination thereof). Other suitablematerials for use as a metallic liner and metallic fill material arewithin the contemplated scope of disclosure. Various etch stopdielectric layers and dielectric capping layers may be inserted betweenvertically neighboring pairs of ILD layers 30, or may be incorporatedinto one or more of the ILD layers 30.

While the present disclosure is described employing an embodiment inwhich the array 95 of non-volatile memory cells and TFT selector devicesmay be formed as a component of a third interconnect-level structure L3,embodiments are expressly contemplated herein in which the array 95 ofnon-volatile memory cells and TFT selector devices may be formed ascomponents of any other interconnect-level structure (e.g., L1-L7).Further, while the present disclosure is described using an embodimentin which a set of eight interconnect-level structures are formed,embodiments are expressly contemplated herein in which a differentnumber of interconnect-level structures is used. In addition,embodiments are expressly contemplated herein in which two or morearrays 95 of non-volatile memory cells and TFT selector devices may beprovided within multiple interconnect-level structures in the memoryarray region 50. While the present disclosure is described employing anembodiment in which an array 95 of non-volatile memory cells and TFTselector devices may be formed in a single interconnect-level structure,embodiments are expressly contemplated herein in which an array 95 ofnon-volatile memory cells and TFT selector devices may be formed overtwo vertically adjoining interconnect-level structures.

FIGS. 2A-2H are each vertical cross-sectional views illustrating thesteps of a method of forming an FE structure 200, which may be includedin the array 95 of FIG. 1C, according to various embodiments of thepresent disclosure. Referring to FIG. 2A, a first dielectric layer 110may be deposited over a substrate 100. The substrate 100 may be anysuitable substrate, such as a semiconductor device substrate, and mayinclude control elements formed during FEOL processes. In someembodiments, one or more additional dielectric layers, such as ILDlayers, may be deposited between the substrate 100 and the firstdielectric layer 110. In such embodiments, the first dielectric layer110 may be omitted.

The first dielectric layer 110 may be formed of any suitable dielectricmaterial such as silicon oxide (SiO₂), or the like, or high-k dielectricmaterials such as silicon nitride (SiN₄), hafnium oxide (HfO₂), hafniumsilicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titaniumoxide (HfTiO), hafnium zirconium oxide (Hf_(0.5)Zr_(0.5)O₂), tantalumoxide (Ta₂O₅), aluminum oxide (Al₂O₃), hafnium dioxide-alumina(HfO₂—Al₂O₃), zirconium oxide (ZrO₂), or the like. In some embodiments,the first dielectric layer 110 may be a native oxide layer formed on thesubstrate 100. Other suitable dielectric materials may also be withinthe contemplated scope of disclosure.

The first dielectric layer 110 may be deposited using any suitabledeposition process. Herein, suitable deposition processes may includechemical vapor deposition (CVD), physical vapor deposition (PVD), atomiclayer deposition (ALD), high density plasma CVD (HDPCVD), metalorganicCVD (MOCVD), plasma enhanced CVD (PECVD), sputtering, laser ablation, orthe like.

Referring to FIG. 2B, a bottom electrode layer 120L may be deposited onthe first dielectric layer 110. For example, the bottom electrode layer120L may be deposited on the upper surface of the first electric layer110, such that the bottom electrode layer 120L contacts a top surface ofthe first dielectric layer 110.

In some embodiments, the bottom electrode layer may be embedded in thefirst dielectric layer 110. For example, the first dielectric layer 110may be patterned to form trenches, an electrically conductive materialmay be deposited in the trenches, and a planarization process may beperformed to planarize upper surfaces of the bottom electrode layer 120Land the first dielectric layer 110.

The bottom electrode layer 120L may include any suitable electricallyconductive material, such as copper (Cu), aluminum (Al), zirconium (Zr),titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta),tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd),platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), alloys thereof,and/or a combination thereof. Other suitable metallic materials withinthe contemplated scope of disclosure may also be used. For example, thebottom electrode material layer 120L may include, and/or may consistessentially of, an elemental metal such as W, Cu, Ti, Ta, Ru, Co, Mo, orPt. The bottom electrode layer 120L may be deposited using any suitabledeposition process. For example, suitable deposition processes mayinclude physical vapor deposition (PVD), sputtering, chemical vapordeposition (CVD), atomic layer deposition (ALD), plasma-enhancedchemical vapor deposition (PECVD), or combinations thereof. Thethickness of the bottom electrode layer 120L may be in a range from 10nm to 100 nm, although lesser and greater thicknesses may also be used.

Referring to FIG. 2C, a high-k dielectric layer 124L may be deposited onthe bottom electrode layer 120L. Herein, high-k dielectric materialshave a dielectric constant greater than 3.9 and may include, but are notlimited to, silicon nitride (SiN_(x)), hafnium oxide (HfO₂), hafniumsilicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titaniumoxide (HfTiO), hafnium zirconium oxide (Hf_(0.5)Zr_(0.5)O₂) (HZO)),tantalum oxide (Ta₂O₅), aluminum oxide (Al₂O₃), lanthanum aluminate(LaAlO₃), hafnium dioxide-alumina (HfO₂—Al₂O₃), zirconium oxide (ZrO₂),magnesium oxide (MgO), combinations thereof, or the like. Other suitabledielectric materials are within the scope of the present disclosure. Thehigh-k dielectric layer 124L may be deposited using any suitabledeposition processes, as described above.

Referring to FIG. 2D, an FE layer 126L (also referred to as anFE/dielectric layer 126 or dielectric layer 126) may be grown on thehigh-k dielectric layer 124. The FE layer 126L may be formed of anysuitable ferroelectric material, such as HfO, HfO₂, ZrO₂,Hf_(0.5)Zr_(0.5)O₂ (HfZrO), HfSiO, HfLaO, AlScN, PbZrO₃ (PBT),Pb[Zr_(x)Ti_(1-x)]O₃, (0≤x≤1) (PZT), Pb_(1-x)La_(x)Zr_(1-y)Ti_(y)O₃(PLZT), BaTiO₃, PbTiO₃, PbNb₂O₆, LiNbO₃, LiTaO₃, PbMg_(1/3)Nb_(2/3)O₃(PMN), PbSc_(1/2)Ta_(1/2)O₃ (PST), SrBi₂Ta₂O₉ (SBT),Bi_(1/2)Na_(1/2)TiO₃, combinations thereof, or the like. In someembodiments, the FE layer 126L may be formed of HfO. HfO₂, HfZrO, PZT,PbTiO₃, HfLaO, or the like. Other suitable ferroelectric materials arewithin the contemplated scope of disclosure. Alternatively, the FE layer126L may be formed by depositing an FE material using any suitabledeposition method, such as PVD, spin coating and annealing, sputtering,CVD, ALD, PECVD, spray pyrolysis, pulsed laser deposition (PLD) orcombinations thereof. In various embodiments, the FE 126 may be aferroelectric film that is thin enough to allow tunneling of electronsthere through. For example, the thickness of the FE layer 126L may beabout 1 nm to about 50 nm thick, such as from about 2 nm to about 25 nm,or about 10 nm thick.

The orthorhombic phase may be the primary crystal phase of the FE layer126L. For HfO based FE materials, at least 50 at %, such as from about60 at % to about 99.9 at %, or from about 70 at % to about 95 at % ofthe FE layer 126L may have an orthorhombic crystal structure. In someembodiments, a tetragonal phase for PBT and/or PZT may be the primarycrystalline phase for the FE layer 126L. In some embodiments, the FElayer 126L may be thermally annealed to further improve the crystalstructure thereof. For example, the FE layer 126L may be annealed usingExcimer-laser annealing (ELA), flash lamp annealing (FLA), furnaceannealing, or the like.

Referring to FIG. 2E, an interface metal layer 128L may be formed on theFE layer 126L. The interface metal layer 128L may include a metalconfigured to promote the formation of a desired crystal structure, suchas an orthorhombic crystal structure, in a layer formed thereon. Forexample, the interface metal layer 128L may comprise tungsten (W),molybdenum (Mo), ruthenium (Ru), tantalum nitride (TaN), combinationsthereof, or the like. The interface metal layer 128L may be depositedusing any suitable deposition processes, such as CVD, PVD, or the like.The interface metal layer 128L may have thickness ranging from 0.5angstrom (A) to 10 A, such as from about 1-8 A.

In some embodiments, an optional anneal process may be performed afterdepositing the interface metal layer 128L. For example, the interfacemetal layer 128L may be deposited over the FE layer 126L, and anannealing process may be performed to induce the orthorhombic phase inthe FE layer 126L. Other thermal or anneal processes may be performed inany subsequent back-end-of-line (BEOL) to induce the orthorhombic phasein the FE. For example, the interface metal layer 128L may be annealedusing Excimer-laser annealing (ELA), flash lamp annealing (FLA), furnaceannealing, or the like. The annealing process in a BEOL position may beperformed at a temperature below 500° C., such as at a temperatureranging from about 250° C. to about 450° C. In other FEOL or MEOL, theannealing process may be performed at higher temperatures to induce theorthorhombic phase in the FE layer 126L.

Referring to FIG. 2F, a top electrode layer 130L may be deposited on theFE layer 126L. The top electrode layer 130L may include, and/or mayconsist essentially of, at least one of a transition metal, a conductivemetallic nitride, and a conductive metallic carbide. Exemplary metallicmaterials that may be used for the top electrode layer 130L include, butare not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, analloy thereof, and/or a combination thereof. Other suitable materialswithin the contemplated scope of disclosure may also be used. Forexample, the top electrode layer 130L may include, and/or may consistessentially of, an elemental metal such as W, Cu, Ti, Ta, Ru, Co, Mo, orPt. The thickness of the top electrode layer 130L may be in a range from10 nm to 100 nm, although lesser and greater thicknesses may also beused. In some embodiments, the interface metal layer 128L and the topelectrode layer 130L may have the same material and may be regarded asthe same metal layer.

Referring to FIG. 2G, the layered structure (120L, 124L, 126L, 128L,130L formed in FIG. 2F may be patterned to form at least one memorycells 200. For example, the bottom electrode layer 120L, the high-kdielectric layer 124L, the FE layer 126L, interface metal layer 128L,and the top electrode layer 130L may be etched or otherwise patterned toforma a memory cell 200 consisting of a material stack (bottom electrode120, high-k dielectric 124, FE 126, interface metal 128, and topelectrode 130).

A metallic hard mask 162 may be used to pattern the various layers toform the memory cell 200. For example, the metallic hard mask 162 mayinclude a metallic etch stop material that provides high resistance toan anisotropic etch process to be subsequently used to etch a dielectricmaterial (which may include, for example, undoped silicate glass, adoped silicate glass, or organosilicate glass). In one embodiment, themetallic hard mask 162 may include a conductive metallic nitridematerial (such as TiN, TaN, or WN) or a conductive metallic carbidematerial (such as TiC, TaC, or WC). Other suitable metallic hard maskmaterials are within the contemplated scope of disclosure. The metallichard mask 162 may be deposited by chemical vapor deposition or physicalvapor deposition. The thickness of the metallic hard mask 162 may be ina range from 2 nm to 20 nm, such as from 3 nm, to 10 nm, although lesserand greater thicknesses may also be used.

An etch mask (not shown) may be formed over a metallic hard maskmaterial layer to form the metallic hard mask 162. For example, the etchmask may include an array of patterned photoresist material portionsthat are formed by applying and lithographically patterning aphotoresist material layer. Each patterned photoresist material portionmay have a horizontal cross-sectional shape of a circle, a rectangle, arounded rectangle, an ellipse, or any other closed curvilinear shape.

An anisotropic etch process may be performed to transfer the pattern inthe etch mask and through the layer stack (120L, 124L, 126L, 128L, 130L)including the metallic hard mask material layer, the top electrode layer130L, the interface metal layer 128L, the FE layer 126L, the high-kdielectric layer 124L, and the bottom electrode layer 120L. Theanisotropic etch process etches unmasked portions of the layer stack(120L, 124L, 126L, 128L, 130L), and forms an array of FTJ memory cells200.

Each FTJ memory cell 200 includes a vertical stack including a bottomelectrode 120, a high-k dielectric 124, an FE 126, an interface metal128, a top electrode 130, and a metallic hard mask portion 162. In oneembodiment, the etch mask may be consumed during the anisotropic etchprocess, and the metallic hard mask portions 162 may be used as anadditional etch mask during patterning of the bottom electrode layer120L. Each metallic hard mask portion 162 is a patterned portion of themetallic hard mask material layer. Each top electrode 130 is a patternedportion of the top electrode layer 160L. Each interface metal 128 is apatterned portion of the interface metal layer 128L. Each FE 126 is apatterned portion of the FE layer 126L. Each high-k dielectric 124 is apatterned portion of the high-k dielectric layer 124L. Each bottomelectrode 120 is a patterned portion of the bottom electrode layer 120L.

The sidewalls of the layers within each ferroelectric tunnel junctionmemory cell 200 may be vertically coincident, i.e., may be locatedwithin a vertical plane including sidewalls of at least one overlyinglayer and/or at least one underlying layer. The sidewalls of the layerswithin each ferroelectric tunnel junction memory cell 200 may bevertical, or may have a taper angle in a range from 0.1 degree to 30degrees. The etch mask and/or metallic hard mask portion 162 may besubsequently removed, for example, by ashing. Optionally, dielectricspacers (not shown) may be formed around the array of ferroelectrictunnel junction memory cells 300.

Referring to FIG. 2H, a second dielectric layer 112 (e.g., aninterconnect dielectric layer), may be deposited on the first dielectriclayer 110, covering the memory cell 200. In particular, the seconddielectric layer 112 may be formed of any suitable dielectric material,such as silicon oxide, using any suitable deposition process asdescribed herein. In some embodiments, the second dielectric layer 112may be omitted. In some embodiments, the memory cell 200 may beencapsulated before depositing the second dielectric layer 112. In otherembodiments, such as shown and described below with reference to FIG. 7, the memory cell 200 may be coupled with a select transistor. Theselect transistor may be a conventional planar CMOS transistor, a finFETtransistor, TFT or any other suitable select transistor. The selecttransistor may be fabricated in a FEOL, MEOL or BEOL process.

FIG. 3A is a vertical cross-sectional view of an alternative embodimentmemory cell 300 when formed by an alternate method. Referring to FIG.3A, a first dielectric layer 110 deposited on a substrate 100. The firstdielectric layer 110 may be patterned to form a trench, for example, byphotolithography. A bottom electrode layer (e.g., 120L) may be depositedin the trench to form a bottom electrode 120. A planarization process,such as chemical mechanical planarization (CMP) process, may beperformed to planarize upper surfaces of the first dielectric layer 110and the bottom electrode 120.

A second dielectric layer 112 may be deposited on the first dielectriclayer 110 and the bottom electrode 120. The second dielectric layer 112may be patterned to form a trench that exposes a top surface of thebottom electrode 120. A high-k dielectric layer (e.g., 124L) may bedeposited in the trench and on the bottom electrode layer 120 to form ahigh-k dielectric 124, such that a bottom surface of the high-kdielectric 124 is in contact with a top surface of the bottom electrode120. A planarization process, such as CMP, may be performed to planarizeupper surfaces of the high-k dielectric 124 and the second dielectriclayer 112.

A third dielectric layer 114 may be deposited on the second dielectriclayer 112 and the high-k dielectric layer 124. The third dielectriclayer 114 may be patterned to form a trench that exposes a top surfaceof the high-k dielectric 124. An FE layer (e.g., 126L) may be depositedon the high-k dielectric layer 124 and in the trench to form an FE 126,such that a bottom surface of the FE 126 is in contact with a topsurface of the high-k dielectric 124. A planarization process, such asCMP, may be performed to planarize upper surfaces of the FE layer 126and the third dielectric layer 114.

A fourth dielectric layer 116 may be deposited on the third dielectriclayer 114 and the FE 126. The fourth dielectric layer 116 may bepatterned to form a trench that exposes a top surface of the FE 126. Aninterface metal layer (e.g., 128L) may be deposited on the FE 126 and inthe trench to form an interface metal 128, such that a bottom surface ofthe interface metal 128 is in contact with a top surface of the FE 126.A planarization process, such as CMP, may be performed to planarizeupper surfaces of the interface metal 128 and the fourth dielectriclayer 116.

A fifth dielectric layer 118 may be deposited on the fourth dielectriclayer 116 and the interface metal 128. The fifth dielectric layer 118may be patterned to form a trench that exposes a top surface of theinterface metal 128. A top electrode layer (e.g., 130L) may be depositedon the interface metal 128 and in the trench to form a top electrode130, such that a bottom surface of the top electrode 130 is in contactwith a top surface of the interface metal 128. A planarization process,such as CMP, may be performed to planarize upper surfaces of the topelectrode 130 and the fifth dielectric layer 118.

FIG. 3B is a vertical cross-sectional view of the memory cell 200 whenformed by an alternate method. Referring to FIG. 3B, a memory cell 200may be formed as discussed above with respect to FIGS. 2A-2H. Anencapsulation layer 140 may be formed on the memory cell 200 using anencapsulation material and any suitable deposition process. For example,suitable encapsulation materials may include silicon nitride, aluminumoxide, or the like. A second dielectric layer 112 may then be optionallydeposited on the encapsulation layer 140. For example, after thedeposition of the encapsulation layer 140, the second dielectric layer112 may be deposited over the structure 200 and encapsulation layer 140.The second dielectric layer 112 may be subsequently planarized asdiscussed above.

FIGS. 4A-4G are vertical cross-sectional views showing a method offorming a FeFET 400, according to various embodiments of the presentdisclosure. For illustrative purposes, the process described in FIGS.4A-4G implement an etching and CMP similar to the processes of FIG. 3Aas described. In some embodiments, the structure as illustrated in FIG.4G may be formed using processes similar to those in FIGS. 2-2H asdescribed.

Referring to FIG. 4A, a semiconductor layer 102 may be formed on asemiconductor substrate 100, such as an amorphous silicon or polysiliconsubstrate. The semiconductor layer 102 may include a source region 104and a drain region 106, which may be formed by doping portions of thesubstrate 100 with P or N-type impurities. For example, the source anddrain regions 104, 106 may be formed by ion-implantation processes, orthe like. A channel region 108 of the transistor 300 may be disposedbetween the source region 104 and drain region 106. The channel region108 may include P or N-type impurities that are different from the P orN-type impurities doped into the source region 104 and drain region 106,such that the channel region 108 has a different conductivity-type thanthe source region 104 and drain region 106. In alternative embodiments,the semiconductor layer 102 may utilize other suitable semiconductormaterials such as polysilicon, amorphous silicon, or a semiconductingoxide, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO,InSnO, GaOx, InOx, or the like to form the channel region 108 and othernon-silicon materials to form the source region 104 and drain region106.

Referring to FIG. 4B, a first dielectric layer 110 may be formed on thesemiconductor layer 102. The first dielectric layer 110 may be patternedto form a trench 170 that exposes a top surface of the channel region108. For example, a photoresist layer (not shown) may be applied overthe first dielectric layer 110. The photoresist layer may then bepatterned for example, using photolithography techniques such thatportions of the first dielectric layer 110 disposed over the channelregion 108 are exposed. The exposed portions of the first dielectriclayer 110 may be etched to form trench 170.

Referring to FIG. 4C, an FE layer (e.g., 126L) may be deposited on thechannel region 108 and in the trench 170 to form an FE 126, such that abottom surface of the FE 126 is in contact with a top surface of thechannel region 108. A planarization process, such as CMP, may beperformed to remove any excess FE material and to planarize uppersurfaces of the FE 126 and the first dielectric layer 110 to beco-planar. The FE 126 may be formed of materials and processes asdescribed above with regard to FIG. 2E.

Referring to FIG. 4D, a second dielectric layer 112 may be deposited andpatterned over the FE 126 and the first dielectric layer 110. In asimilar manner as described above, the second dielectric layer 112 maybe patterned to form a trench 172 that exposes a top surface of the FE126.

Referring to FIG. 4E, an interface metal layer (e.g., 128L) may bedeposited on the channel region 108 and in the trench 172 to form aninterface metal 128, such that a bottom surface of the interface metal128 is in contact with a top surface of the FE 126. A planarizationprocess, such as CMP, may be performed to planarize upper surfaces ofthe interface metal 128 and the second dielectric layer 112.

The FE 126 may have an orthorhombic crystal structure resulting frombeing in contact with the interface metal 128. The orthorhombic phasemay be the primary crystal phase of the FE 126. In particular, at least50 at %, such as from about 60 at % to about 99.9 at %, or from about 70at % to about 95 at % of the FE layer 130 may have an orthorhombiccrystal structure.

Referring to FIG. 4F, a third second dielectric layer 114 may be formedon the interface metal 128 and the second dielectric layer 112. In asimilar manner as described above, the third dielectric layer 114 may bepatterned to form a trench 174 that exposes a top surface of theinterface metal 128.

Referring to FIG. 4G, a gate electrode layer may be deposited on theinterface metal and in the trench 174 to form a gate electrode 132, suchthat a bottom surface of the gate electrode 132 is in contact with a topsurface of the interface metal 128. A gate electrode 132 may be formedon the FE layer 126. The gate electrode 132 may include an electricallyconductive material, and may be formed by any suitable depositionprocess, as described above with respect to the bottom and topelectrodes 120 and 130. In some embodiments, the gate electrode 132 mayinclude an N-type work function material, such as Ta, TiAl, etc., or mayinclude a P-type work function material, such as TiN, WO₃, etc. The workfunction of the gate electrode 132 may be selected based on theconductivity type of the channel region 108. A planarization process,such as CMP, may be performed to planarize the upper surfaces of thegate electrode 132 and the third dielectric layer 114.

In various embodiments, the source region 104 may be electricallyconnected to a source electrode or bit line through contact vias (notshown). The drain region 106 may be electrically connected to a drainelectrode through contact vias (not shown). The gate electrode 132 maybe electrically connected to a word line of a semiconductor device, suchas a memory device.

FIGS. 5A and 5B are vertical cross-sectional views of an alternativemethod of forming a transistor 400, according to various embodiments ofthe present disclosure. Referring to FIG. 5A, an FE layer 126L may bedeposited on a substrate 100 including a semiconductor structure 102including a source region 104, a drain region 106, and a channel region108. An interface metal layer 128L may be deposited on the FE layer126L, and a gate electrode material layer 132L may be deposited on theinterface metal layer 128L. A patterned photoresist layer 160 may bedeposited over the gate electrode material layer 132L and patternedusing photolithography techniques.

Referring to FIGS. 5A and 5B, the FE layer 126L, the interface metallayer 128L, and the gate electrode material layer 132L may be etched,using the photoresist layer 160 as a mask, to form an FE 126, andinterface metal 128, and a gate electrode 132. A first dielectric layer110 may be deposited on the resulting structure. In particular, a firstdielectric layer 110 may be deposited on the substrate 100 so as tocover the source region 104, the drain region 106, and the gateelectrode 132. A planarization process, such as CMP, may be performed toplanarize top surfaces of the first dielectric layer 110 and the gateelectrode 132.

In other embodiments, the gate electrode 132 may be formed using areplacement gate process. For example, the gate electrode 132 may formedto include a sacrificial material layer such as a p-doped polysiliconmaterial, n-doped polysilicon material, a silicon-germanium alloy,amorphous carbon or a dielectric material. In a subsequent processingstep, the sacrificial material layer may be replaced with a highconductive metal layer. FIGS. 6A-6C are a vertical cross-sectional viewsshowing a method of forming of a transistor 500, according to variousother embodiments of the present disclosure. Referring to FIG. 6A,similar to other embodiments described herein, a semiconductor structure102 may be formed on a semiconductor substrate 100, such as an amorphoussilicon or polysilicon substrate. The semiconductor structure 102 mayinclude a source region 104 and a drain region 106, which may be formedby doping portions of the substrate 100 with P or N-type impurities. Forexample, the source and drain regions 104, 106 may be formed byion-implantation processes, or the like. A channel region 108 of thetransistor 400 may be disposed between the source and drain regions 104,106. The channel region 108 may include P or N-type impurities that aredifferent from the P or N-type impurities doped into the source anddrain regions 104, 106, such that the channel region 108 has a differentconductivity-type than the source regions 104 and drain regions 106.

In alternative embodiments, the semiconductor layer 102 may utilizeother suitable semiconductor materials such as polysilicon, amorphoussilicon, or a semiconducting oxide, such as InGaZnO (IGZO), indium tinoxide (ITO), InWO, InZnO, InSnO, GaOx, InOx, or the like to form thechannel region 108 and other non-silicon materials to form the sourceregion 104 and drain region 106.

According to various embodiments, the semiconductor structure 102 may beformed using a replacement gate process. In particular, a replacementgate 502 (e.g., a dummy gate) may be formed on the substrate 100,covering the channel region 108. The replacement gate 502 may be formedby depositing a polysilicon material, for example, by physical vapordeposition (PVD) or chemical vapor deposition (CVD). The depositedmaterial may be patterned and etched (e.g., wet or dry etched) to formthe replacement gate 502. In embodiments that use doped source and drainregions, an ion implantation process may then be performed, using thereplacement gate 502 as a mask, to dope the semiconductor substrate 100with impurities and form the source and drain regions 104, 106. In otherembodiments, the replacement gate 502 may be used as a hard mask to formcavities to deposit the non-silicon materials (i.e., metals) to form thesource regions 104 and drain regions 106.

Referring to FIG. 6B, the first dielectric layer 110 may be formed onthe semiconductor structure 102. For example, the first dielectric layer110 may be formed over the replacement gate 502, the resulting structuremay optionally be planarized, and then the replacement gate 502 may beremoved to form the trench 170.

Referring to FIG. 6C, an FE layer (e.g., 126L) may be conformallydeposited on the channel region 108 and in the trench 170 to form an FE126, such that a bottom surface of the FE 126 is in contact with a topsurface of the channel region 108. The conformal deposition may resultin U-shaped layers in which the FE layer 126 may also be deposited onthe sidewalls of the first dielectric layer 110.

An interface metal layer (e.g., 128L) may be conformally deposited onthe channel region 108 and in the trench 170 to form an interface metal128, such that a bottom surface of the interface metal 128 is in contactwith a top surface of the FE 126. The conformal deposition may result inU-shaped layers in which the interface metal 128 may also be depositedon the sidewalls of the FE layer 126. As noted above, the FE 126 mayhave an orthorhombic crystal structure resulting from being in contactwith the interface metal 128. The orthorhombic phase may be the primarycrystal phase of the FE 126. In particular, at least 50 at %, such asfrom about 60 at % to about 99.9 at %, or from about 70 at % to about 95at % of the FE layer 130 may have an orthorhombic crystal structure.

A gate electrode layer may be conformally deposited on the interfacemetal 128 and in the trench 170 to form a gate electrode 132, such thata bottom surface of the gate electrode 132 is in contact with a topsurface of the interface metal 128. The gate electrode 132 may includean electrically conductive material, and may be formed by any suitabledeposition process, as described above with respect to the bottom andtop electrodes 120 and 130. In some embodiments, the gate electrode 132may include an N-type work function material, such as Ta, TiAl, etc., ormay include a P-type work function material, such as TiN, WO₃, etc. Thework function of the gate electrode 132 may be selected based on theconductivity type of the channel region 108.

A planarization process, such as CMP, may be performed to planarize theupper surfaces of the gate electrode 132, interface metal layer 128, theFE layer 126 and the first dielectric layer 110.

In various embodiments, the source region 104 may be electricallyconnected to a source electrode or bit line through contact vias (notshown). The drain region 106 may be electrically connected to a drainelectrode through contact vias (not shown). The gate electrode 132 maybe electrically connected to a word line of a semiconductor device, suchas a memory device.

In some embodiments, the source and drain regions 104, 106 may be formedby depositing a doped metal layer on the substrate 100 overlapping withthe channel region 108, or in trenches formed adjacent to the channelregion 108. The metal layer may include metals such as Sc, Ti, Cr, Ni,Al, Nb, Pd, Pt, Au, Ag, or the like, and may be formed using anysuitable method, such as PVD, CVD, ALD, or the like.

In some embodiments, after depositing the metal layer, an annealingprocess, such as a rapid thermal annealing process, may be performed,such that the metal diffuses into the substrate 100 and forms the sourceand drain regions 104, 106. In some embodiments, the metal may form ametal silicide in the source and drain regions 104, 106. The annealingprocess may be performed at a temperature below 500° C., such as at atemperature ranging from about 250° C. to about 450° C. The metal layermay be subsequently removed, for example, by selective etching. In otherembodiments, the metal layer may be patterned to form source and drainelectrodes.

While the transistor 500 is depicted as having a top-gate configuration,the present disclosure is not limited thereto. For example, in otherembodiments, the transistor 500 may have a bottom-gate configuration.

FIG. 7A is a partially transparent perspective view of a transistor 600,according to various embodiments of the present disclosure. FIG. 7B is avertical cross-sectional view taken along line B-B of FIG. 7A. FIG. 7Cis a vertical cross-sectional view taken along line C-C of FIG. 7A. Thetransistor 600 is similar to the transistor 400 of FIGS. 4G and 5B aswell as transistor 500 of FIG. 6C. Accordingly, only the differencesthere between will be described in detail.

Referring to FIGS. 7A-7C, the transistor 600 may be a ferroelectric finfield-effect transistor (FinFET). In some embodiments, the transistor600 may operate as a memory structure. The semiconductor structure 102may be in the form of a “fin” that extends vertically from the surfaceof a semiconductor substrate 100. The semiconductor structure 102includes a source region 104, a drain region 106, and a channel region108 disposed there between.

The transistor 600 may include an FE 126 disposed on the channel region108. The FE 126 may be otherwise similar to the FE 126 of the transistor400 of FIGS. 4G and 5B. In various embodiments, the FE 126 may bedisposed on multiple surfaces of the channel region 108, such as on thetop and opposing side surfaces of the channel region 108.

The transistor 600 may include an interface metal 128 disposed on the FE126. In particular, the interface metal 128 may be disposed on the FE126, with the interface metal 128 promoting the formation of anorthorhombic structure of the FE 126. The interface metal 128 may beotherwise similar to the interface metal 128 of the transistor 400 ofFIG. 4 . In various embodiments, the interface metal 128 may be disposedon multiple surfaces of the FE 126, such as on the top and opposing sidesurfaces of the FE 126 (as illustrated in FIG. 5B).

The transistor 600 may include a gate electrode 132 disposed on theinterface metal 128. The gate electrode 132 may be otherwise similar tothe gate electrode 132 of the transistor 400 of FIGS. 4G and 5B. Invarious embodiments, the gate electrode 132 may be disposed on multiplesurfaces of the interface metal 128, such as on the top and opposingside surfaces of the interface metal 128 (as illustrated in FIG. 6B).

The transistor 600 may include a dielectric layer 134, such as an oxidelayer, that surrounds a portion of the semiconductor layer 102 adjacentto the substrate 100. In particular, the dielectric layer 134 may beconfigured to insulate the gate electrode 132, the interface metal 128,and/or the FE 126 from the substrate 100 and/or channel region 108.

FIG. 8 is a vertical cross-sectional view of a FeRAM memory structure700, according to various embodiments of the present disclosure. Thememory structure 700 may be included in a memory device, such as thememory device of FIGS. 1A-1C. The memory structure 700 may include atransistor 710 and an FTJ memory cell 720. Accordingly, the memorystructure 700 may have a 1 transistor-1 capacitor (1T-1C) configuration.Any other suitable configuration including more than one transistorand/or more than one capacitor are within the scope of the presentdisclosure. For example, a memory structure may include a 2T/2Cconfiguration.

The transistor 710 may be disposed on a substrate 702. The substrate 702may be a semiconductor substrate, such as an amorphous silicon orpolysilicon substrate. In other embodiments, the substrate 702 may be adielectric layer, such as an interconnect dielectric layer.

The transistor 710 may include a semiconductor layer 102 including asource region 104, a drain region 106, and a channel region 108 disposedthere between. The semiconductor layer 102 may be formed of polysilicon,amorphous silicon, or a semiconducting oxide, such as InGaZnO (IGZO),indium tin oxide (ITO), InWO, InZnO, InSnO, GaOx, InO_(x), or the like.Accordingly, the transistor 710 may be a CMOS transistor, if thesubstrate 702 is an amorphous silicon or polysilicon substrate, and thetransistor may be a TFT transistor, if the substrate 702 is a layerformed during a BEOL process. In embodiments in which the transistor 710is a FEOL transistor, the channel region 108 may be formed of silicon,or a compound including silicon. In embodiments in which the transistor710 is a BEOL transistor, the channel region 108 may be formed of asemiconducting oxide, such as InGaZnO (IGZO), indium tin oxide (ITO),InWO, InZnO, InSnO, GaOx, InO_(x), or the like.

A high-k dielectric layer 732 may be disposed on the channel region 108.In various embodiments, the high-k dielectric layer 732 may have athickness (t_(hk)) in the range of 0.5-5.0 nm, such as 1-4 nm, althoughgreater or lesser thicknesses may be used.

A gate electrode 132 may be disposed on the high-k dielectric layer 732.The gate electrode 132 may be formed of any suitable electricallyconductive material, using any suitable deposition process, as describedherein.

The FTJ 720 may be similar to the memory cell 200 shown in FIG. 2H, theFTJ 300 shown in FIG. 3A, or the FTJ 302 shown in FIG. 3B. Accordingly,the FTJ 720 may include a bottom electrode 120, a high-k dielectric 124,an FE 126, an interface metal 128, and a top electrode layer 130, whichmay be formed as described above.

The source region 104 may be electrically connected to a bit line 740,the drain region 106 may be electrically connected to the bottomelectrode layer 120 by a drain via contact 742, and the top electrodelayer 130 may be electrically coupled to a plate line 744. The gateelectrode 132 may be electrically connected to a word line 746. Adielectric layer 730, such as an interconnect dielectric layer, may bedisposed on the substrate 702. In particular, the high-k dielectriclayer 124, gate electrode 132, word line 744, bit line 740, drain viacontact 742, and FTJ 720 may be embedded in the dielectric layer 730.

FIG. 9 is a flow chart illustrating steps of a method of forming an FTJ200 or FTJ 300 as shown in FIGS. 2H and 3A, according to variousembodiments of the present disclosure. Referring to FIGS. 2A-2H and 3A,in step 801, a bottom electrode layer 120L may be deposited on asubstrate, such as a dielectric layer 110. The bottom electrode layer120L may be formed by depositing an electrically conductive material,such as copper, aluminum (Al), zirconium (Zr), titanium (Ti), titaniumnitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN),molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt(Co), nickel (Ni), iridium (Ir), alloys thereof, or the like. In someembodiments, the bottom electrode may be formed of TiN, Ru, W, Mo, TaN,or the like.

The bottom electrode layer 120L may be formed using any suitabledeposition process. For example, suitable deposition processes mayinclude PVD), sputtering, CVD, atomic layer deposition (ALD), PECVD, orcombinations thereof. In some embodiments, the top electrode layer 130may be formed of TiN, Ru, W, Mo, TaN, or the like.

In step 802, a high-k dielectric layer 124L may be deposited on thebottom electrode layer 120L. The high-k dielectric layer 124L may beformed of a high-k material such as silicon nitride (SiN_(x)), hafniumoxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium tantalum oxide(HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide(Hf_(0.5)Zr_(0.5)O₂) (HZO)), tantalum oxide (Ta₂O₅), aluminum oxide(Al₂O₃), lanthanum aluminate (LaAlO₃), hafnium dioxide-alumina(HfO₂—Al₂O₃), zirconium oxide (ZrO₂), magnesium oxide (MgO),combinations thereof, or the like. Other suitable dielectric materialsare within the scope of the present disclosure. The high-k dielectriclayer 124L may be deposited using any suitable deposition processes, asdescribed above. In some embodiments, the high-k dielectric layer 124Lmay comprise Al₂O₃, MgO, LaAlO₃, or the like.

In step 803, an FE layer 126L may be deposited on the high-k dielectriclayer 124. The FE layer 126L may be formed using any suitable depositionprocess, using any suitable FE material, as described herein such as,HfO₂, ZrO₂, Hf_(0.5)Zr_(0.5)O₂ (HfZrO), HfSiO, HfLaO, AlScN, PbZrO₃,Pb[Zr_(x)Ti_(1-x)]O₃, (0≤x≤) (PZT), Pb_(1-x)La_(x)Zr_(1-y)Ti_(y)O₃(PLZT), BaTiO₃, PbTiO₃, PbNb₂O₆, LiNbO₃, LiTaO₃, PbMg_(1/3)Nb_(2/3)O₃(PMN), PbSc_(1/2)Ta_(1/2)O₃ (PST), SrBi₂Ta₂O₉ (SBT),Bi_(1/2)Na_(1/2)TiO₃, combinations thereof, or the like. In someembodiments, the FE layer 126L may be formed of HfO₂, HfZrO, PZT,PbTiO₃, HfLaO, or the like.

In step 804, an interface metal layer 128L may be deposited over the FElayer 126L. The interface metal layer 128L may include a metalconfigured to promote the formation of a desired crystal structure in alayer formed thereon. For example, the interface metal layer 128L maycomprise W, Mo, Ru, TaN, combinations thereof, or the like. Theinterface metal layer 128L may be deposited using any suitabledeposition processes, such as CVD, PVD, or the like. The interface metallayer 128L may have thickness ranging from 0.5 A to 10 A, such as fromabout 1-8 A.

In some embodiments, an anneal process may be performed after depositingthe interface metal layer 128L. For example, the interface metal layer128L may be deposited over the FE layer 126L, and an annealing processmay be performed to induce the orthorhombic phase in the FE layer 126L.Other thermal or anneal processes may be performed in any subsequentBEOL to induce the orthorhombic phase in the FE.

In step 805, a top electrode layer 130L may be formed on the interfacemetal layer 128L. The top electrode layer 130L may be formed of anelectrically conductive material, using processes as described withrespect to the bottom electrode layer 120L.

In step 806, the structure formed in steps 801-805 may be patterned toform one or more FTJs 200 or 300. In particular, a photoresist materialand/or one or more hard mask/etch mask layers may be deposited on thetop electrode layer 130L, patterned using a photolithographic process toform a patterned photoresist layer, and then portions exposed throughthe photoresist layer of the structure may be etched using a wet or dryetching process.

In step 807, the method may optionally include covering the FTJ 200 witha dielectric layer, using any suitable dielectric material and anysuitable deposition process.

FIG. 10 is a flow chart illustrating steps of a method of formingtransistors 400, 500, 600, as shown in FIGS. 4G, 6C, 7A, and 7B,according to various embodiments of the present disclosure. Referring toFIGS. 4G, 6C, 7A, 7B, and 10 , in step 901 a semiconductor layer 102 maybe formed on a substrate 100. For example, in embodiments in which thetransistor may be formed in a FEOL position, the channel region 108 maybe formed from silicon. The source region 104 and drain region 106 maybe formed by implanting dopants, such as by an ion implantation process.In embodiments in which the transistor may be formed in a BEOL position,the channel region 108 may be formed from of a semiconducting oxide,such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO,GaOx, InO_(x), or the like. The source region 104 and drain region 106may be formed from a metal material. Referring to FIGS. 4A-4C, in step902, an FE 126 may be formed on the channel region 108 within adielectric layer 110. Referring to FIGS. 4D and 4E, in step 903, aninterface metal 128 may be formed on the FE 126 within a dielectriclayer 112. Referring to FIGS. 4F and 4G, in step 904, a gate electrode132 may be deposited on the interface metal 128.

Various embodiments provide a memory device 200, 300, 600 comprising aferroelectric (FE) structure including a dielectric layer 124L, an FElayer 126L disposed on the dielectric layer 124L, and an interface metallayer 128L disposed on the FE layer 126L, wherein the interface metallayer 128L is configured to induce a formation of an orthorhombiccrystal phase in the FE layer 126L. The memory device may furtherinclude a top electrode layer 130L disposed on the interface metal layer128L.

In one embodiment, the interface metal layer 128L may include W, Mo, Ru,TaN, or a combination thereof to induce the FE layer 126L to have theorthorhombic phase. In one embodiment, the top electrode layer 130L andthe interface metal layer 128L may be the same material. In oneembodiment, the interface metal layer 128L may have a thickness of 1-8A. In one embodiment, the FE layer 126L may include HfO, HfO2, HfZrO,Pb[ZrxTi1-x]O3, (0≤x≤1), PbTiO3, HfLaO, or a combination thereof. In oneembodiment, a primary phase of the FE layer 126L may be orthorhombic andinduced by an anneal process on the interface metal layer 128L. In oneembodiment, the memory device may further include a bottom electrodelayer 120L, in which the dielectric layer 124L is disposed on the bottomelectrode layer 120L to dispose the FE structure (124L, 126L, 128L)between the bottom electrode layer 120L and the top electrode layer130L. In one embodiment, dielectric layer 124L may include AlO, MgO,LaAlO3, or a combination thereof.

In one embodiment, the memory device may further include a substrate 702and a transistor 710 disposed on the substrate 702, in which thetransistor 710 may include a source region (104/106) and a drain region(104/106) formed in the substrate 702, a channel region 108 formed inthe substrate 702 between the source and drain regions (104/106), ahigh-k dielectric layer 732 disposed on the channel region 108, and agate electrode 132 disposed on the high-k dielectric layer 732. In oneembodiment, the bottom electrode layer 120L is electrically connected tothe source region or the drain region (104/106). In one embodiment, thememory device may further include a bit line 740 electrically coupled tothe source region 104, a drain via contact 742 electrically coupled tothe drain region 106 and the bottom electrode layer 120L; and a wordline 746 electrically coupled to the gate electrode 132.

Various embodiments provide a transistor 400, 600 a source region 104, adrain region 106, and a channel region 108 disposed between the sourceregion 104 and the drain region 106, an FE layer 126L disposed on thechannel region 108, an interface metal layer 128L disposed on the FElayer 126L, wherein the interface metal layer 128L is configured toinduce a formation of an orthorhombic crystal phase in the FE layer, anda gate electrode 132 disposed on the interface metal layer 128L. In oneembodiment, the interface metal layer 128L may include W, Mo, Ru, TaN,or a combination thereof to induce the FE layer 126L to have theorthorhombic phase. In one embodiment, the gate electrode 132 and theinterface metal layer 128L may be the same material. In one embodiment,the interface metal layer 128L may have a thickness of 1-8 A. In oneembodiment, the FE layer 126L may comprise HfO, HfO2, HfZrO,Pb[ZrxTi1-x]O3, (0≤x≤1), PbTiO3, HfLaO, or a combination thereof. In oneembodiment, the transistor 400, 600 may be a FinFET, such that theinterface metal layer 128L surrounds multiple walls of the FE layer126L.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A memory device, comprising: a ferroelectric (FE)structure comprising: a dielectric layer; an FE layer disposed on thedielectric layer; and an interface metal layer disposed on the FE layer,wherein the interface metal layer is configured to induce a formation ofan orthorhombic crystal phase in the FE layer; and a top electrode layerdisposed on the interface metal layer.
 2. The memory device of claim 1,wherein the interface metal layer comprises tungsten (W), molybdenum(Mo), ruthenium (Ru), tantalum nitride (TaN), or a combination thereofto induce the FE layer to have the orthorhombic crystal phase.
 3. Thememory device of claim 1, wherein the top electrode layer and theinterface metal layer are a same material.
 4. The memory device of claim1, wherein the interface metal layer has a thickness of 1-8 A.
 5. Thememory device of claim 1, wherein the FE layer comprises HfO, HfO₂,HfZrO, Pb[Zr_(x)Ti_(1-x)]O₃, (0≤x≤1), PbTiO₃, HfLaO, or a combinationthereof.
 6. The memory device of claim 5, wherein a primary phase of theFE layer is orthorhombic and induced by an anneal process on theinterface metal layer.
 7. The memory device of claim 1, wherein thedielectric layer comprises AlO, MgO, LaAlO₃, or a combination thereof.8. The memory device of claim 1, further comprising: a bottom electrodelayer, wherein the dielectric layer is disposed on the bottom electrodelayer such that the FE layer is disposed between the bottom electrodelayer and the top electrode layer.
 9. The memory device of claim 8,further comprising: a substrate; and a transistor disposed on thesubstrate, the transistor comprising: a source region and a drain regionformed in the substrate; a channel region formed in the substratebetween the source and drain regions; a high-k dielectric layer disposedon the channel region; and a gate electrode disposed on the high-kdielectric layer; wherein the bottom electrode layer is electricallyconnected to the drain region.
 10. The memory device of claim 9, furthercomprising: a bit line electrically coupled to the source region; adrain via contact electrically coupled to the drain region and thebottom electrode layer; and a word line electrically coupled to the gateelectrode.
 11. A transistor comprising: a semiconductor layer comprisinga source region, a drain region, and a channel region disposed betweenthe source region and the drain region; a ferroelectric (FE) layerdisposed on the channel region; an interface metal layer disposed on theFE layer, wherein the interface metal layer is configured to induce aformation of an orthorhombic crystal phase in the FE layer; and a gateelectrode disposed on the interface metal layer.
 12. The transistor ofclaim 11, wherein the interface metal layer comprises tungsten (W),molybdenum (Mo), ruthenium (Ru), tantalum nitride (TaN), or acombination thereof to induce the FE layer to have the orthorhombiccrystal phase.
 13. The transistor of claim 11, wherein the gateelectrode and the interface metal layer are a same material.
 14. Thetransistor of claim 11, wherein the interface metal layer has athickness of 1-8 A.
 15. The transistor of claim 11, wherein the FE layercomprises HfO, HfO₂, HfZrO, Pb[Zr_(x)Ti_(1-x)]O₃, (0≤x≤1), PbTiO₃,HfLaO, or a combination thereof.
 16. The transistor of claim 11, whereinthe transistor is a fin field-effect transistor, such that the interfacemetal layer surrounds multiple surfaces of the FE layer.
 17. A memorystructure, comprising: a bottom electrode layer; a ferroelectric (FE)structure comprising: a dielectric layer disposed on the bottomelectrode layer; an FE layer disposed on the dielectric layer; and aninterface metal layer disposed on the FE layer, wherein the interfacemetal layer is configured to induce a formation of an orthorhombiccrystal phase in the FE layer; a top electrode layer disposed on theinterface metal layer; a substrate; and a transistor disposed on thesubstrate, the transistor comprising: a source region and a drain regionformed in the substrate; a channel region formed in the substratebetween the source and drain regions; a high-k dielectric layer disposedon the channel region; and a gate electrode disposed on the high-kdielectric layer, wherein the bottom electrode layer is electricallyconnected to the drain region.
 18. The memory structure of claim 17,further comprising: a bit line electrically coupled to the sourceregion; a drain via contact electrically coupled to the drain region andthe bottom electrode layer; and a word line electrically coupled to thegate electrode.
 19. The memory structure of claim 17, wherein theinterface metal layer comprises tungsten (W), molybdenum (Mo), ruthenium(Ru), tantalum nitride (TaN), or a combination thereof to induce the FElayer to have the orthorhombic crystal phase.
 20. The memory structureof claim 17, wherein the top electrode layer and the interface metallayer are a same material.